CLK_CAPTURE_MODE=USE_RISING_CLOCK_EDG, CLKGEN_MODE=USE_CLOCK_INTERNALLY, PARALLEL_MODE=SHIFT_1_BIT_PER_CLOC, INV_QUALIFIER=USE_NORMAL_QUALIFIER, INV_OUT_CLK=NORMAL_CLOCK, DATA_CAPTURE_MODE=DETECT_RISING_EDGE, MATCH_MODE=DO_NOT_MATCH_DATA
Slice multiplexer configuration registers.
| MATCH_MODE | Match mode. Selects whether the match filter is active or whether data is captured. 0 (DO_NOT_MATCH_DATA): Do not match data. 1 (MATCH_DATA): Match data. |
| CLK_CAPTURE_MODE | Capture clock mode 0 (USE_RISING_CLOCK_EDG): Use rising clock edge. 1 (USE_FALLING_CLOCK_ED): Use falling clock edge. |
| CLKGEN_MODE | Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock. 0 (USE_CLOCK_INTERNALLY): Use clock internally generated by COUNTER. 1 (USE_EXTERNAL_CLOCK_F): Use external clock from a pin or other slice. |
| INV_OUT_CLK | Invert output clock 0 (NORMAL_CLOCK): Normal clock. 1 (INVERTED_CLOCK): Inverted clock. |
| DATA_CAPTURE_MODE | Condition for input bit match interrupt 0 (DETECT_RISING_EDGE): Detect rising edge. 1 (DETECT_FALLING_EDGE): Detect falling edge. 2 (DETECT_LOW_LEVEL): Detect LOW level. 3 (DETECT_HIGH_LEVEL): Detect HIGH level. |
| PARALLEL_MODE | Parallel mode 0 (SHIFT_1_BIT_PER_CLOC): Shift 1 bit per clock. 1 (SHIFT_2_BITS_PER_CLO): Shift 2 bits per clock. 2 (SHIFT_4_BITS_PER_CLO): Shift 4 bits per clock. 3 (SHIFT_1_BYTE_PER_CLO): Shift 1 byte per clock. |
| INV_QUALIFIER | Inversion qualifier 0 (USE_NORMAL_QUALIFIER): Use normal qualifier. 1 (USE_INVERTED_QUALIFI): Use inverted qualifier. |
| RESERVED | Reserved. |